Reapply "[ARM] Combine base-updating/post-incrementing vector load/stores."
authorAhmed Bougacha <ahmed.bougacha@gmail.com>
Sat, 13 Dec 2014 23:22:12 +0000 (23:22 +0000)
committerAhmed Bougacha <ahmed.bougacha@gmail.com>
Sat, 13 Dec 2014 23:22:12 +0000 (23:22 +0000)
commit0cb861634b680b76985a5fbd7240fe3084884daf
tree3e95d8400dcbe978ef36e59541158bdcfc34b9f7
parent1fda216122e43d0385a08ba7abeaf71823f27f34
Reapply "[ARM] Combine base-updating/post-incrementing vector load/stores."

r223862 tried to also combine base-updating load/stores.
r224198 reverted it, as "it created a regression on the test-suite
on test MultiSource/Benchmarks/Ptrdist/anagram by scrambling the order
in which the words are shown."
Reapply, with a fix to ignore non-normal load/stores.
Truncstores are handled elsewhere (you can actually write a pattern for
those, whereas for postinc loads you can't, since they return two values),
but it should be possible to also combine extloads base updates, by checking
that the memory (rather than result) type is of the same size as the addend.

Original commit message:
We used to only combine intrinsics, and turn them into VLD1_UPD/VST1_UPD
when the base pointer is incremented after the load/store.

We can do the same thing for generic load/stores.

Note that we can only combine the first load/store+adds pair in
a sequence (as might be generated for a v16f32 load for instance),
because other combines turn the base pointer addition chain (each
computing the address of the next load, from the address of the last
load) into independent additions (common base pointer + this load's
offset).

Differential Revision: http://reviews.llvm.org/D6585

llvm-svn: 224203
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/test/CodeGen/ARM/alloc-no-stack-realign.ll
llvm/test/CodeGen/ARM/memcpy-inline.ll
llvm/test/CodeGen/ARM/vector-load.ll [new file with mode: 0644]
llvm/test/CodeGen/ARM/vector-store.ll [new file with mode: 0644]
llvm/test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll