csky: Add memory layout 2.5G(user):1.5G(kernel)
authorGuo Ren <guoren@linux.alibaba.com>
Mon, 7 Sep 2020 06:20:18 +0000 (06:20 +0000)
committerGuo Ren <guoren@linux.alibaba.com>
Tue, 12 Jan 2021 01:52:40 +0000 (09:52 +0800)
commit0c8a32eed1625a65798286fb73fea8710a908545
tree69992b6e217f5e985ebbf1f739b2af336d89138c
parent7c53f6b671f4aba70ff15e1b05148b10d58c2837
csky: Add memory layout 2.5G(user):1.5G(kernel)

There are two ways for translating va to pa for csky:
 - Use TLB(Translate Lookup Buffer) and PTW (Page Table Walk)
 - Use SSEG0/1 (Simple Segment Mapping)

We use tlb mapping 0-2G and 3G-4G virtual address area and SSEG0/1
are for 2G-2.5G and 2.5G-3G translation. We could disable SSEG0
to use 2G-2.5G as TLB user mapping.

Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
19 files changed:
arch/csky/Kconfig
arch/csky/abiv1/inc/abi/ckmmu.h
arch/csky/abiv2/inc/abi/ckmmu.h
arch/csky/abiv2/inc/abi/entry.h
arch/csky/include/asm/memory.h
arch/csky/include/asm/mmu_context.h
arch/csky/include/asm/page.h
arch/csky/include/asm/pgalloc.h
arch/csky/include/asm/pgtable.h
arch/csky/include/asm/processor.h
arch/csky/include/asm/segment.h
arch/csky/kernel/atomic.S
arch/csky/kernel/entry.S
arch/csky/kernel/head.S
arch/csky/kernel/setup.c
arch/csky/kernel/smp.c
arch/csky/kernel/vmlinux.lds.S
arch/csky/mm/fault.c
arch/csky/mm/init.c