drm/i915/icl: Add Wa_1406609255
authorRadhakrishna Sripada <radhakrishna.sripada@intel.com>
Thu, 4 Oct 2018 18:29:38 +0000 (11:29 -0700)
committerMika Kuoppala <mika.kuoppala@linux.intel.com>
Tue, 9 Oct 2018 07:00:29 +0000 (10:00 +0300)
commit0c7d2aedf51b0a9f728ec6e921eaa8f82a47db91
tree7744f84cb3b19d4901a072eafeaf4ddd5e867aa4
parentf53a70bd93f6058d178421d82ebd3c549159f12f
drm/i915/icl: Add Wa_1406609255

Shader feature to prefetch binding tables does not support 16:6 18:8 BTP
formats. Enabling fault handling could result in hangs with faults.
Disabling demand prefetch would disable binding table prefetch.

V2: Fix the stepping rivision to B0(Mika)

References: HSDES#1406609255, HSDES#1406573985
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181004182939.7668-5-radhakrishna.sripada@intel.com
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_workarounds.c