[AMDGPU] Resolve issues when picking between ds_read/write and ds_read2/write2
authorMirko Brkusanin <Mirko.Brkusanin@amd.com>
Thu, 10 Dec 2020 11:40:49 +0000 (12:40 +0100)
committerMirko Brkusanin <Mirko.Brkusanin@amd.com>
Thu, 10 Dec 2020 11:40:49 +0000 (12:40 +0100)
commit0c7cce54eba3249489530040f41103dd8e0049f7
tree54704dddd1e1a8ed4217ecc6550861575885270c
parentbedf3a0f507113bb09acaa317c533d85fe52518a
[AMDGPU] Resolve issues when picking between ds_read/write and ds_read2/write2

Both ds_read_b128 and ds_read2_b64 are valid for 128bit 16-byte aligned
loads but the one that will be selected is determined either by the order in
tablegen or by the AddedComplexity attribute. Currently ds_read_b128 has
priority.

While ds_read2_b64 has lower alignment requirements, we cannot always
restrict ds_read_b128 to 16-byte alignment because of unaligned-access-mode
option. This was causing ds_read_b128 to be selected for 8-byte aligned
loads regardles of chosen access mode.

To resolve this we use two patterns for selecting ds_read_b128. One
requires alignment of 16-byte and the other requires
unaligned-access-mode option.

Same goes for ds_write2_b64 and ds_write_b128.

Differential Revision: https://reviews.llvm.org/D92767
llvm/lib/Target/AMDGPU/AMDGPU.td
llvm/lib/Target/AMDGPU/DSInstructions.td
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local-128.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/lds-misaligned-bug.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.128.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll
llvm/test/CodeGen/AMDGPU/load-local.128.ll
llvm/test/CodeGen/AMDGPU/store-local.128.ll