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(parent: d20830d) | patch
[ARM] check bitwidth in PerformORCombine
authorSaleem Abdulrasool <compnerd@compnerd.org>
Tue, 30 Jul 2013 04:43:08 +0000 (04:43 +0000)
committerSaleem Abdulrasool <compnerd@compnerd.org>
Tue, 30 Jul 2013 04:43:08 +0000 (04:43 +0000)
commit0c2ee5a2cbcaeed4c1b2a2d0cbcd6a37406b9292
treea79a8a12b2b9c48ef989f497363bb085b4edc167tree | snapshot
parentd20830dfe5062392f3af702aecb54c731f40777ecommit | diff
[ARM] check bitwidth in PerformORCombine

When simplifying a (or (and B A) (and C ~A)) to a (VBSL A B C) ensure that the
bitwidth of the second operands to both ands match before comparing the negation
of the values.

Split the check of the value of the second operands to the ands.  Move the cast
and variable declaration slightly higher to make it slightly easier to follow.

Bug-Id: 16700
Signed-off-by: Saleem Abdulrasool <compnerd@compnerd.org>
llvm-svn: 187404
llvm/lib/Target/ARM/ARMISelLowering.cpp diff | blob | history
llvm/test/CodeGen/ARM/2013-07-29-vector-or-combine.ll [new file with mode: 0644] blob
Domain: System / Toolchain;