[PowerPC] Switch to by-name matching for instructions (part 2 of 2).
authorJames Y Knight <jyknight@google.com>
Tue, 8 Nov 2022 22:11:08 +0000 (17:11 -0500)
committerJames Y Knight <jyknight@google.com>
Thu, 2 Feb 2023 20:28:45 +0000 (15:28 -0500)
commit0be684ed97397ef06c1ba391df0cf84b87edb792
tree6c08336457b00bd3a5e4a9a4adbdf417c5cdc52a
parent4b43ef3e5c37459996ce0f53615881f436cb0e65
[PowerPC] Switch to by-name matching for instructions (part 2 of 2).

This is a follow-on to https://reviews.llvm.org/D134073.

Currently, all of the "memri"-style complex operands, which contain
both a register and an immediate, are encoded into a single field in
the instruction definition. This requires complex encoders/decoders,
and instruction definitions that insert and extract the correct parts
of the bits.

Now, switch to naming and encoding/decoding the sub-operands
separately.

Thus, we can now disable useDeprecatedPositionallyEncodedOperands.

Reviewed By: barannikov88

Differential Revision: https://reviews.llvm.org/D137670
llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/lib/Target/PowerPC/PPCInstrFormats.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCInstrP10.td
llvm/lib/Target/PowerPC/PPCInstrSPE.td
llvm/lib/Target/PowerPC/PPCInstrVSX.td
llvm/lib/Target/PowerPC/PPCRegisterInfo.td