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[RISCV] Specify registers used in DWARF exception handling
authorAlex Bradbury <asb@lowrisc.org>
Mon, 8 Jul 2019 09:16:47 +0000 (09:16 +0000)
committerAlex Bradbury <asb@lowrisc.org>
Mon, 8 Jul 2019 09:16:47 +0000 (09:16 +0000)
commit0b9addb8c0cce6cd8f8d36f6ea8ebf2403dbcdf5
tree9b0ad7261c6a8a3fbe3b0e8f05dfc082202d5b97tree | snapshot
parent4ec445b813a1d479e3d9f9226c265fad66fd8f8ccommit | diff
[RISCV] Specify registers used in DWARF exception handling

Defines RISCV registers for getExceptionPointerRegister() and
getExceptionSelectorRegister().

Differential Revision: https://reviews.llvm.org/D63411
Patch by Edward Jones.
Modified by Alex Bradbury to add CHECK lines to exception-pointer-register.ll.

llvm-svn: 365301
llvm/lib/Target/RISCV/RISCVISelLowering.cpp diff | blob | history
llvm/lib/Target/RISCV/RISCVISelLowering.h diff | blob | history
llvm/test/CodeGen/RISCV/exception-pointer-register.ll [new file with mode: 0644] blob
Domain: System / Toolchain;