intel/fs: fix incorrect register flag interaction with dynamic interpolator mode
authorLionel Landwerlin <lionel.g.landwerlin@intel.com>
Tue, 21 Nov 2023 08:38:19 +0000 (10:38 +0200)
committerEric Engestrom <eric@engestrom.ch>
Sun, 3 Dec 2023 07:59:40 +0000 (07:59 +0000)
commit0b7f91be9d1a16433d4a598490542f459bbfa761
tree66bf607b51e46e284e2a3fe822d3c97696ae446d
parent9fdc28451d1ef03258ab0322d6800e38254982a5
intel/fs: fix incorrect register flag interaction with dynamic interpolator mode

Once NIR code is lowered and a few optimization passes have run, there
might be flag register interactions between instructions quite far
away from one another.

In the following case :

   f0 = and r0, r1
   ...
   fs_interpolate r2, r3
   ...
   if f0
      ...
   endif

If we lower fs_inteporlate while using the f0 register, we completely
garble the value meant for the if block.

To fix this, emit the predication for fs_interpolate in brw_fs_nir.cpp
when doing the NIR translation to the backend IR. This will guarantee
that the flag register interactions are visible to the optimization
passes, avoiding the problem above.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 68027bd38e ("intel/fs: implement dynamic interpolation mode for dynamic persample shaders")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9757
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26306>
(cherry picked from commit 83a1657b6c7f117f1226a955b8d2f1e01b22d322)
.pick_status.json
src/intel/compiler/brw_eu_defines.h
src/intel/compiler/brw_fs_nir.cpp
src/intel/compiler/brw_lower_logical_sends.cpp