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(parent: 99b2c85) | patch
i965: Don't emit register spill offsets directly into g0.
authorEric Anholt <eric@anholt.net>
Thu, 21 Oct 2010 21:40:49 +0000 (14:40 -0700)
committerEric Anholt <eric@anholt.net>
Thu, 21 Oct 2010 22:21:28 +0000 (15:21 -0700)
commit0b77d57394a3712851ec271aa7ad353d56f302a1
tree1255d015a64b25903a39323709cf9ec3e53d0268tree | snapshot
parent99b2c8570ea6f46c6564681631f0e0750a0641cccommit | diff
i965: Don't emit register spill offsets directly into g0.

g0 is used by others, and is expected to be left exactly as it was
dispatched to us.  So manually move g0 into our message reg when
spilling/unspilling and update the offset in the MRF.  Fixes failures
in texture sampling after having spilled a register.
src/mesa/drivers/dri/i965/brw_eu_emit.c diff | blob | history
Domain: Graphics System / GL;