clk: tegra: Add PLL post divider table
authorPeter De Schrijver <pdeschrijver@nvidia.com>
Wed, 3 Apr 2013 14:40:39 +0000 (17:40 +0300)
committerStephen Warren <swarren@nvidia.com>
Thu, 4 Apr 2013 22:10:45 +0000 (16:10 -0600)
commit0b6525acd13f2d33cd3be86d0dbd2ddd1ffeda8f
tree989c920b532d4d5d7372c275ed828356cff9c581
parent7ba28813b41120dd67329fd04dc732ea7fef05a0
clk: tegra: Add PLL post divider table

Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider.
Introduce a table based approach and switch PLLU to it.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
drivers/clk/tegra/clk-pll.c
drivers/clk/tegra/clk-tegra20.c
drivers/clk/tegra/clk-tegra30.c
drivers/clk/tegra/clk.h