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(parent: f97ace5) | patch
RegisterScavenger: Allow fail without spill
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Mon, 25 Feb 2019 20:29:04 +0000 (20:29 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Mon, 25 Feb 2019 20:29:04 +0000 (20:29 +0000)
commit0b148574153c797466298cc3a5b37471862ae290
treedb56839b2a339ee7e33e64e1507e39c22eda6757tree | snapshot
parentf97ace5639863bde1eb4cc9081d191896657b56bcommit | diff
RegisterScavenger: Allow fail without spill

AMDGPU wants to use this in some contexts where
the spilling is either impossible, or a worse alternative
to doing something else.

llvm-svn: 354816
llvm/include/llvm/CodeGen/RegisterScavenging.h diff | blob | history
llvm/lib/CodeGen/RegisterScavenging.cpp diff | blob | history
Domain: System / Toolchain;