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(parent: 8de9423) | patch
drm/amd/display: DP YCbCr 4:2:0 support
authorEric Bernstein <eric.bernstein@amd.com>
Mon, 14 May 2018 21:01:00 +0000 (17:01 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 15 Jun 2018 17:20:27 +0000 (12:20 -0500)
commit0b126112e90a96907aa14c39374fc7bfdbba131a
tree3a6a2e3704fb79d088650cfbef67341058bd4140tree | snapshot
parent8de94233f4cdcd5b3065fa9b9af3edc10874a120commit | diff
drm/amd/display: DP YCbCr 4:2:0 support

Update MSA MISC1 bit 6 programming to handle YCbCr 4:2:0
and BT2020 cases.

Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c diff | blob | history
Domain: System / Kernel;