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[RISCV] Optimize (seteq (i64 (and X, 0xffffffff)), C1)
authorCraig Topper <craig.topper@sifive.com>
Mon, 18 Jul 2022 16:58:54 +0000 (09:58 -0700)
committerCraig Topper <craig.topper@sifive.com>
Mon, 18 Jul 2022 17:54:45 +0000 (10:54 -0700)
commit0b0275289961dd49315bcb3b8dfcae5687f23eaa
tree640e122cc92ab7afca222570eb837ac87d3513a5tree | snapshot
parent464b3a9d8a1a86b53278c2ecc59db78dcaf0593fcommit | diff
[RISCV] Optimize (seteq (i64 (and X, 0xffffffff)), C1)

(and X, 0xffffffff) requires 2 shifts in the base ISA. Since we
know the result is being used by a compare, we can use a sext_inreg
instead of an AND if we also modify C1 to have 33 sign bits instead
of 32 leading zeros. This can also improve the generated code for
materializing C1.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D129980
llvm/lib/Target/RISCV/RISCVISelLowering.cpp diff | blob | history
llvm/test/CodeGen/RISCV/i64-icmp.ll diff | blob | history
Domain: System / Toolchain;