clk: renesas: Add r8a774c0 CPG Core Clock Definitions
authorFabrizio Castro <fabrizio.castro@bp.renesas.com>
Wed, 12 Sep 2018 10:41:52 +0000 (11:41 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Wed, 19 Sep 2018 14:41:00 +0000 (16:41 +0200)
commit0acb6b53df36b8453be4fc2563e37e84450eed25
tree9a151ec3ba43a5cf8cb2df9db0c2924e532df6a2
parent016f9663156fe7e1402ef5ebaaca55d67f639966
clk: renesas: Add r8a774c0 CPG Core Clock Definitions

Add all RZ/G2E (a.k.a. R8A774C0) Clock Pulse Generator Core
Clock Outputs, as listed in Table 8.2g ("List of Clocks
[RZ/G2E]") of the RZ/G2 Hardware User's Manual.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
include/dt-bindings/clock/r8a774c0-cpg-mssr.h [new file with mode: 0644]