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(parent: c4ca10f) | patch
fsl-ddr: Fix power-down timing settings
authorDave Liu <daveliu@freescale.com>
Wed, 16 Dec 2009 16:24:36 +0000 (10:24 -0600)
committerKumar Gala <galak@kernel.crashing.org>
Tue, 5 Jan 2010 19:49:10 +0000 (13:49 -0600)
commit0a71c92c7e1e565111cb34cd389a21ec500ca5c1
treeabee130bc9075de43eb494b30e102a907ffda992tree | snapshot
parentc4ca10f1db36c3ce649c656dec14f7aab644dd86commit | diff
fsl-ddr: Fix power-down timing settings

1. TIMING_CFG_0[ACT_PD_EXIT] was set to 6 clocks, but
   It should be set to tXP parameter, tXP=max(3CK, 7.5ns)
2. TIMING_CFG_0[PRE_PD_EXIT] was set to 6 clocks, but
   It should be set to tXP (if MR0[A12]=1) else to tXPDLL parameter
   We are setting the mode register MR0[A12]='1'

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
cpu/mpc8xxx/ddr/ctrl_regs.c diff | blob | history
Domain: System / Kernel;