drm/nv50-/disp: move DP link training to core and train from supervisor
authorBen Skeggs <bskeggs@redhat.com>
Tue, 19 Feb 2013 04:17:53 +0000 (23:17 -0500)
committerBen Skeggs <bskeggs@redhat.com>
Wed, 20 Feb 2013 06:01:02 +0000 (16:01 +1000)
commit0a0afd282fd715dd63d64b243299a64da14f8e8d
tree2ab42981dd69f24fba45b72ec842b64288b76661
parent5cc027f6b1ec651c18a4322ed3e30c6e9cf01e96
drm/nv50-/disp: move DP link training to core and train from supervisor

We need to be able to do link training for PIOR-connected ANX9805 from
the third supervisor handler (due to script ordering in the bios, can't
have the "user" call train because some settings are overwritten from
the modesetting bios scripts).

This moves link training for SOR-connected DP encoders to the second
supervisor interrupt, *before* we call the modesetting scripts (yes,
different ordering from PIOR is necessary).  This is useful since we
should now be able to remove some hacks to workaround races between
the supervisor and link training paths.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
15 files changed:
drivers/gpu/drm/nouveau/Makefile
drivers/gpu/drm/nouveau/core/engine/disp/dport.c [new file with mode: 0644]
drivers/gpu/drm/nouveau/core/engine/disp/dport.h [new file with mode: 0644]
drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
drivers/gpu/drm/nouveau/core/engine/disp/nv50.h
drivers/gpu/drm/nouveau/core/engine/disp/nv94.c
drivers/gpu/drm/nouveau/core/engine/disp/nva3.c
drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
drivers/gpu/drm/nouveau/core/engine/disp/nve0.c
drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c
drivers/gpu/drm/nouveau/core/engine/disp/sornv94.c
drivers/gpu/drm/nouveau/core/engine/disp/sornvd0.c
drivers/gpu/drm/nouveau/core/include/core/class.h
drivers/gpu/drm/nouveau/nouveau_dp.c
drivers/gpu/drm/nouveau/nv50_display.c