dt-bindings: Renesas versaclock7 device tree bindings
authorAlex Helms <alexander.helms.jy@renesas.com>
Mon, 12 Sep 2022 18:36:12 +0000 (11:36 -0700)
committerStephen Boyd <sboyd@kernel.org>
Sat, 1 Oct 2022 00:34:20 +0000 (17:34 -0700)
commit09d1855656dad04127aee195baf2eedae029175d
treee3af56557df45f9fc76ac97a56cde964c2fdb3b4
parent568035b01cfb107af8d2e4bd2fb9aea22cf5b868
dt-bindings: Renesas versaclock7 device tree bindings

Renesas Versaclock7 is a family of configurable clock generator ICs
with fractional and integer dividers. This driver has basic support
for the RC21008A device, a clock synthesizer with a crystal input and
8 outputs. The supports changing the FOD and IOD rates, and each
output can be gated.

Signed-off-by: Alex Helms <alexander.helms.jy@renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220912183613.22213-2-alexander.helms.jy@renesas.com
Tested-by: Saeed Nowshadi <saeed.nowshadi@amd.com>
[sboyd@kernel.org: Rename nodes in example to generic names]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Documentation/devicetree/bindings/clock/renesas,versaclock7.yaml [new file with mode: 0644]
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