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author	Ron Lieberman <Ron.Lieberman@amd.com>
	Wed, 22 Dec 2021 16:39:28 +0000 (11:39 -0500)
committer	Ron Lieberman <Ron.Lieberman@amd.com>
	Wed, 22 Dec 2021 16:39:28 +0000 (11:39 -0500)
commit	09b53296cf1649d6f953e71d1c3cd970ad74dde8
tree	ec8fa49d767e58e38a4e6a0ab44c549d28952dfb	tree \| snapshot
parent	ea22fdd120aeb1bbb9ea96670d70193dc02b2c5f	commit \| diff

Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range"

This reverts commit 9075009d1fd5f2bf9aa6c2f362d2993691a316b3.

Failed amdgpu runtime buildbot # 3514

97 files changed:

llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp		diff \| blob \| history
llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td		diff \| blob \| history
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp		diff \| blob \| history
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h		diff \| blob \| history
llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td		diff \| blob \| history
llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp		diff \| blob \| history
llvm/lib/Target/AMDGPU/SIISelLowering.cpp		diff \| blob \| history
llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp		diff \| blob \| history
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp		diff \| blob \| history
llvm/lib/Target/AMDGPU/SIInstructions.td		diff \| blob \| history
llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp		diff \| blob \| history
llvm/lib/Target/AMDGPU/SIRegisterInfo.td		diff \| blob \| history
llvm/lib/Target/AMDGPU/SOPInstructions.td		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-post-legalize.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-pre-legalize.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-illegal-types.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constantexpr.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constrained-fp.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fixed-function-abi-vgpr-args.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-getelementptr.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-memory-intrinsics.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-metadata.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-ptrmask.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sat.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.fmax.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-smed3.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-umed3.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/roundeven.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/amdpal-callable.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/fdiv-nofpexcept.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/fix-frame-ptr-reg-copy-livein.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/fpow.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/fshr.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/indirect-call.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/ipra.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/llvm.powi.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/nested-calls.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/no-remat-indirect-mov.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/reserve-vgpr-for-sgpr-spill.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/save-fp.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/sibling-call.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/splitkit-copy-bundle.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/stack-realign.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/tail-call-amdgpu-gfx.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/udiv.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/udiv64.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/urem-seteq-illegal-types.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/urem64.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/wave32.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll		diff \| blob \| history
llvm/test/CodeGen/MIR/AMDGPU/machine-metadata.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/AMDGPU/stack-id-assert.mir		diff \| blob \| history

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