[SPARC] Simplify instruction decoder.
authorJames Y Knight <jyknight@google.com>
Mon, 21 Nov 2022 01:41:42 +0000 (20:41 -0500)
committerJames Y Knight <jyknight@google.com>
Wed, 7 Dec 2022 19:37:08 +0000 (14:37 -0500)
commit099001979fe82a069d5572dffea472b339878c75
tree6e0c4413427c4e070956695a9e1de4f41d5f8e52
parent372240dfe3d5a933d9585663e15c4b6173ff23c8
[SPARC] Simplify instruction decoder.

After https://reviews.llvm.org/D137653 named sub-operands can be used
in the auto-generated instruction decoders. This allows the
auto-generated decoders to work properly, so all the hand-coded
decoders in the sparc target can be removed.

In some instances, a manually-written decoder had not been implemented
for an instruction, and thus that instruction was not decoded
properly. These have been fixed (and tests added).

Differential Revision: https://reviews.llvm.org/D137727
llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
llvm/lib/Target/Sparc/SparcInstr64Bit.td
llvm/lib/Target/Sparc/SparcInstrInfo.td
llvm/test/MC/Disassembler/Sparc/sparc-coproc.txt [new file with mode: 0644]
llvm/test/MC/Disassembler/Sparc/sparc-mem.txt
llvm/test/MC/Disassembler/Sparc/sparc-special-registers.txt
llvm/test/MC/Disassembler/Sparc/sparc-v9.txt
llvm/test/MC/Disassembler/Sparc/sparc.txt