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[RISCV] Correct alignment settings for vector registers.
authorHsiangkai Wang <kai.wang@sifive.com>
Fri, 15 Jan 2021 03:27:11 +0000 (11:27 +0800)
committerHsiangkai Wang <kai.wang@sifive.com>
Sat, 16 Jan 2021 15:21:29 +0000 (23:21 +0800)
commit098dbf190a5586d02f48b84eb41b93b701cdeb97
tree2d5ab44aadd0c699af6827b27a316532f42201a0tree | snapshot
parenta4e2a5145a29af678139f33e94ab3df0fc973e59commit | diff
[RISCV] Correct alignment settings for vector registers.

According to "9. Vector Memory Alignment Constraints" in V
specification, the alignment of vector memory access is aligned to the
size of the element. In our current implementation, we support ELEN up
to 64. We could assume the alignment of vector registers is 64 under the
assumption.

Differential Revision: https://reviews.llvm.org/D94751
llvm/lib/Target/RISCV/RISCVRegisterInfo.td diff | blob | history
Domain: System / Toolchain;