t104xrdb: Add Errata A_007662, A_008007 workaround in pbi.cfg
authorPriyanka Jain <Priyanka.Jain@freescale.com>
Wed, 17 Sep 2014 10:27:54 +0000 (15:57 +0530)
committerYork Sun <yorksun@freescale.com>
Fri, 14 Nov 2014 19:12:14 +0000 (11:12 -0800)
commit0921de67440ac5dfc3dbf687217cdecc6335f15e
tree89177cc55c1417f668e0b381b3328d68614e123c
parentab06b236f76cfa42f264ee161be190b3e479298f
t104xrdb: Add Errata A_007662, A_008007 workaround in pbi.cfg

-A_007662 states that for x1 link width, PCIe2 controller trains in
 Gen1 speed while configured for Gen2 speed.
 Workaround:Set the width to x1 and speed to Gen2 by writing to
 CCSR registers in PBI phase

-A_008007 states that PVR register may show random value.
 Workaround: Reset PVR register using DCSR space in PBI phase

Add PBI based software workaround for A_007662 and A_008007
in t104x_pbi.cfg. This is required for SPL-based bootloaders
like NAND-boot, SD-boot, SPI-boot

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
board/freescale/t104xrdb/t104x_pbi.cfg