drm/i915: Fix VIDEO_DIP_CTL bit shifts
authorDhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Fri, 5 Oct 2018 18:56:42 +0000 (11:56 -0700)
committerDhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Mon, 29 Oct 2018 19:43:37 +0000 (12:43 -0700)
commit09209662618f9fdc38b8d4da39040c8829fd2d57
tree73e0cf99e8e1e12d4e00748dd8e56c64b4dd0902
parent1ca2b067d07b491bd82bbaf235841b2a9b3d0c09
drm/i915: Fix VIDEO_DIP_CTL bit shifts

The shifts for VSC_SELECT bits are wrong, fix it. Good thing is the
definitions are unused.

v2: Moves definitions in another patch (Manasi)
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Fixes: 7af2be6d54d4 ("drm/i915/icl: Add VIDEO_DIP registers")
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181005185643.31660-1-dhinakaran.pandiyan@intel.com
drivers/gpu/drm/i915/i915_reg.h