MIPS: bugfix of TLB refill optimisation

MIPS: bugfix of TLB refill optimisation

Patch 748e787e replaced SRL(4)->ROTR(2) sequence in TLB refill handler
during loading EntryLo from PTE by a single ROTR(6).
It prevents running MIPS32 kernel on MIPS64 CPU and even running MIPS32
kernel on system with 36 bits physical address CPU, even with 256MB.
That patch just doesn't clear 4 high-order bits 29:26 and CPU tries
to use a high memory due to SW bits in this field.

This patch restores an original SRL+ROTR sequence if CPU is able to use
that 4 bits of physical address (36:32 in 4K system).

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>