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(parent: 7ac1c78) | patch
[X86] Add 512-bit shuffle test cases for concatenating 128/256-bits with zeros in...
authorCraig Topper <craig.topper@intel.com>
Fri, 9 Feb 2018 05:54:31 +0000 (05:54 +0000)
committerCraig Topper <craig.topper@intel.com>
Fri, 9 Feb 2018 05:54:31 +0000 (05:54 +0000)
commit090e41d0cc657ac03c638ceb1610b628a9ef65d1
tree45e9fc966a726730e45181256414bac4f1f9f8batree | snapshot
parent7ac1c780622f847cdadcb5ed82c5ef0f9a6b445ecommit | diff
[X86] Add 512-bit shuffle test cases for concatenating 128/256-bits with zeros in the upper portion.

We should recognize this and just use a mov that will zero the upper bits.

llvm-svn: 324708
llvm/test/CodeGen/X86/vector-shuffle-512-v8.ll diff | blob | history
Domain: System / Toolchain;