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RISC-V: hwprobe: There can only be one first
authorAndrew Jones <ajones@ventanamicro.com>
Wed, 26 Apr 2023 14:13:32 +0000 (16:13 +0200)
committerPalmer Dabbelt <palmer@rivosinc.com>
Wed, 26 Apr 2023 15:58:33 +0000 (08:58 -0700)
commit08dc107594681040587c23a097cfa678e51f5af2
tree10fb0eef0fe5ab93b94e3f5e6a792052d6a4c938tree | snapshot
parent26e7aacb83dfd04330673c5c9ac336560da52bb3commit | diff
RISC-V: hwprobe: There can only be one first

Only capture the first cpu_id in order for the comparison
below to be of any use.

Fixes: ea3de9ce8aa2 ("RISC-V: Add a syscall for HW probing")
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Evan Green <evan@rivosinc.com>
Link: https://lore.kernel.org/r/20230426141333.10063-2-ajones@ventanamicro.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
arch/riscv/kernel/sys_riscv.c diff | blob | history
Domain: System / Kernel;