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author	Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com>
	Fri, 24 Sep 2021 16:53:51 +0000 (09:53 -0700)
committer	Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com>
	Fri, 24 Sep 2021 17:26:11 +0000 (10:26 -0700)
commit	08d7eec06e8cf5c15a96ce11f311f1480291a441
tree	89c51e64c3239318da44befb33b7e6c939682053	tree \| snapshot
parent	e8e2edd8ca88f8b0a7dba141349b2aa83284f3af	commit \| diff

Revert "Allow rematerialization of virtual reg uses"

Reverted due to two distcint performance regression reports.

This reverts commit 92c1fd19abb15bc68b1127a26137a69e033cdb39.

45 files changed:

llvm/include/llvm/CodeGen/TargetInstrInfo.h		diff \| blob \| history
llvm/lib/CodeGen/TargetInstrInfo.cpp		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/remat-sop.mir		diff \| blob \| history
llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll		diff \| blob \| history
llvm/test/CodeGen/ARM/funnel-shift-rot.ll		diff \| blob \| history
llvm/test/CodeGen/ARM/funnel-shift.ll		diff \| blob \| history
llvm/test/CodeGen/ARM/illegal-bitfield-loadstore.ll		diff \| blob \| history
llvm/test/CodeGen/ARM/neon-copy.ll		diff \| blob \| history
llvm/test/CodeGen/Mips/llvm-ir/ashr.ll		diff \| blob \| history
llvm/test/CodeGen/Mips/llvm-ir/lshr.ll		diff \| blob \| history
llvm/test/CodeGen/Mips/llvm-ir/shl.ll		diff \| blob \| history
llvm/test/CodeGen/Mips/llvm-ir/sub.ll		diff \| blob \| history
llvm/test/CodeGen/Mips/tls.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/atomic-rmw.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/atomic-signext.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/mul.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rv32i-rv64i-half.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rv32zbb.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rv32zbp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rv32zbt.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/shifts.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/srem-vector-lkk.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/urem-vector-lkk.ll		diff \| blob \| history
llvm/test/CodeGen/Thumb/dyn-stackalloc.ll		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-disabled-in-loloops.ll		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/varying-outer-2d-reduction.ll		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-loops.ll		diff \| blob \| history
llvm/test/CodeGen/Thumb2/ldr-str-imm12.ll		diff \| blob \| history
llvm/test/CodeGen/Thumb2/mve-float16regloops.ll		diff \| blob \| history
llvm/test/CodeGen/Thumb2/mve-float32regloops.ll		diff \| blob \| history
llvm/test/CodeGen/Thumb2/mve-postinc-dct.ll		diff \| blob \| history
llvm/test/CodeGen/X86/addcarry.ll		diff \| blob \| history
llvm/test/CodeGen/X86/callbr-asm-blockplacement.ll		diff \| blob \| history
llvm/test/CodeGen/X86/dag-update-nodetomatch.ll		diff \| blob \| history
llvm/test/CodeGen/X86/delete-dead-instrs-with-live-uses.mir		diff \| blob \| history
llvm/test/CodeGen/X86/inalloca-invoke.ll		diff \| blob \| history
llvm/test/CodeGen/X86/licm-regpressure.ll		diff \| blob \| history
llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll		diff \| blob \| history
llvm/test/CodeGen/X86/sdiv_fix.ll		diff \| blob \| history

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