intel/compiler: Tighter src and dest size bounds checking for some opcodes
authorIan Romanick <ian.d.romanick@intel.com>
Wed, 12 Oct 2022 22:32:01 +0000 (15:32 -0700)
committerMarge Bot <emma+marge@anholt.net>
Fri, 10 Mar 2023 15:27:17 +0000 (15:27 +0000)
commit08ca862ef842bcd63a23ae6edaf9c4184da3d632
treee11b06ce5d83583fcf96d3b6f131bc9ccc81d6ce
parent0cc7bf63b761a489af8861ebd32a53e8d229fd99
intel/compiler: Tighter src and dest size bounds checking for some opcodes

Enforce the sizes listed in the Skylake PRM:

BFREV:
    source types: *D
    destination types: *D

CBIT:
    source types: UB, UW, UD
    destination types: UD

FBH:
    source types: D, UD
    destination types: UD

FBL:
    source types: UD
    destination types: UD

LZD:
    source types: D, UD
    destination types: UD

v2: Update BFREV commit message documentation. Suggested by Ken.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19042>
src/intel/compiler/brw_fs_nir.cpp
src/intel/compiler/brw_vec4_nir.cpp