projects / platform / upstream / llvm.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: ab9cdf0) | patch
[RISCV] Add more SHXADD patterns where the input is (and (shl/shr X, C2), C1)
authorCraig Topper <craig.topper@sifive.com>
Tue, 5 Jul 2022 23:01:41 +0000 (16:01 -0700)
committerCraig Topper <craig.topper@sifive.com>
Tue, 5 Jul 2022 23:21:47 +0000 (16:21 -0700)
commit088bb8a328e030dfdc74fe464b564e0eb9b3411c
tree6cb468b3f7bb21c3986ed6dfa8f7b8d95681f549tree | snapshot
parentab9cdf09f4f03259e7e75c5187139e6628a37815commit | diff
[RISCV] Add more SHXADD patterns where the input is (and (shl/shr X, C2), C1)

It might be possible to rewrite (and (shl/shr X, C2), C1) in a way
that gives us a left shift that can be folded into a SHXADD.
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp diff | blob | history
llvm/test/CodeGen/RISCV/rv64zba.ll diff | blob | history
Domain: System / Toolchain;