drm/i915: Move the SPLL enabling into hsw_crt_pre_enable
authorDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 25 Jun 2014 19:01:51 +0000 (22:01 +0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 10 Jul 2014 20:05:24 +0000 (22:05 +0200)
commit082717ead9f5836fac1b2757aad38f652cc63636
treee1fb947b22338b0ecdbe131dea29b39207aa865d
parent97b040aa391651793e4d463408c137b81517cc90
drm/i915: Move the SPLL enabling into hsw_crt_pre_enable

The call to intel_ddi_pll_enable in haswell_crtc_mode_set is the only
function that still touches the hardware state from the crtc mode_set
callback on hsw. Since the SPLL isn't ever shared we can easily take
it out into the hsw crt encoder functions.

Temporarily we'll loose a bit of WARN_ON coverage with this, but once
the WRPLLs are switched over that will be restored. For the SPLL
selection add a WARN in the hsw fdi link training code.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
[imre: rebased on patchset version w/o pch/crt/fdi refactoring]
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_crt.c
drivers/gpu/drm/i915/intel_ddi.c