hdmirx: optimize phy pll init sequence [1/1]

hdmirx: optimize phy pll init sequence [1/1]

PD#SWPL-6400

Problem:
hdmirx phy clk_out is not stable,and causes long detection time

Solution:
VLSI provide a new PLL init sequence

Verify:
TL1

Change-Id: I42b98572226aafc8e61e36b6a2e5dfad078fd8fe
Signed-off-by: yicheng shen <yicheng.shen@amlogic.com>