RISC-V: Fix lui relaxation issue with code at address 0.
authorJim Wilson <jimw@sifive.com>
Thu, 15 Aug 2019 19:01:13 +0000 (12:01 -0700)
committerJim Wilson <jimw@sifive.com>
Thu, 15 Aug 2019 19:01:13 +0000 (12:01 -0700)
commit080a488354d63fec9791a26fadd15e0c5246983d
tree9aa728d8b99659e38b8f1eb05a128c8e60e74cb9
parentdb502012fc46b4dd068461aaeafeaa421489c562
RISC-V: Fix lui relaxation issue with code at address 0.

This fixes a problem originally reported at
    https://github.com/riscv/riscv-binutils-gdb/issues/173

If you have code linked at address zero, you can have a lui instruction
loading a value 0x800 which gets relaxed to a c.lui which is valid (c.lui 0x1
followed by addi -0x800).  Relaxation can reduce the value below 0x800 at which
point the c.lui 0x0 is no longer valid.  We can fix this by converting the
c.lui to a c.li which can load 0.

bfd/
* elfnn-riscv.c (perform_relocation) <R_RISCV_RVC_LUI>: If
RISCV_CONST_HIGH_PART (value) is zero, then convert c.lui instruction
to c.li instruction, and use ENCODE_RVC_IMM to set value.

ld/
* testsuite/ld-riscv-elf/c-lui-2.d: New.
* testsuite/ld-riscv-elf/c-lui-2.ld: New.
* testsuite/ld-riscv-elf/c-lui-2.s: New.
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Run the c-lui-2 test.
bfd/ChangeLog
bfd/elfnn-riscv.c
ld/ChangeLog
ld/testsuite/ld-riscv-elf/c-lui-2.d [new file with mode: 0644]
ld/testsuite/ld-riscv-elf/c-lui-2.ld [new file with mode: 0644]
ld/testsuite/ld-riscv-elf/c-lui-2.s [new file with mode: 0644]
ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp