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(parent: aa635f6) | patch
drm/amd/display: Fix detection of 4 lane for DPALT
authorHansen <Hansen.Dsouza@amd.com>
Fri, 1 Oct 2021 14:36:15 +0000 (22:36 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 6 Oct 2021 19:49:49 +0000 (15:49 -0400)
commit07fe77c3ad96917a6d8386e3ae4f3cc37e60d505
tree66da190ad4a5f0bacbc162a75898c9760950537atree | snapshot
parentaa635f6509ce2e086da09d982abd32e3f652608ccommit | diff
drm/amd/display: Fix detection of 4 lane for DPALT

[Why]
DPALT detection for B0 PHY has its own set of RDPCSPIPE registers

[How]
Use RDPCSPIPE registers to detect if DPALT lane is 4 lane

Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Hansen <Hansen.Dsouza@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c diff | blob | history
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.h diff | blob | history
Domain: System / Kernel;