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(parent: 94b575b) | patch
AMDGPU: Correct DS implementation of areLoadsFromSameBasePtr
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Fri, 8 Mar 2019 20:30:50 +0000 (20:30 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Fri, 8 Mar 2019 20:30:50 +0000 (20:30 +0000)
commit07f904befba01b4d7f7ec9d5b1c70e20c6dcbd7d
tree25fd7feed18946d09b607d3c20ae908850c41f69tree | snapshot
parent94b575b23bded5067ad6ba254be3f53b98ed7c6acommit | diff
AMDGPU: Correct DS implementation of areLoadsFromSameBasePtr

This was checking the wrong operands for the base register and the
offsets. The indexes are shifted by the number of output registers
from the machine instruction definition, and the chain is moved to the
end.

llvm-svn: 355722
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp diff | blob | history
llvm/test/CodeGen/AMDGPU/ds-combine-with-dependence.ll diff | blob | history
Domain: System / Toolchain;