[RISCV] Add support for fixed vector mask logic operations.
authorCraig Topper <craig.topper@sifive.com>
Tue, 16 Feb 2021 17:26:22 +0000 (09:26 -0800)
committerCraig Topper <craig.topper@sifive.com>
Tue, 16 Feb 2021 17:34:00 +0000 (09:34 -0800)
commit07ca13fe0766ded6fd69a6729275020e6b4c0b1b
tree6b2db58d23de367475e96e5638109dec2d876329
parent064ada4ec6bb4cb77d809ba366c90ca59e95d4ba
[RISCV] Add support for fixed vector mask logic operations.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D96741
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.h
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll [new file with mode: 0644]