[TableGen] Emit more variant transitions
authorEvandro Menezes <e.menezes@samsung.com>
Fri, 23 Nov 2018 21:17:33 +0000 (21:17 +0000)
committerEvandro Menezes <e.menezes@samsung.com>
Fri, 23 Nov 2018 21:17:33 +0000 (21:17 +0000)
commit079bf4b7b4fc3c2ffeb57b02a580408cd7259bf8
tree791783e2de31fa55adc867101859895218b32553
parent7e32cc83533858716dae4b49b345338e08e695e8
[TableGen] Emit more variant transitions

`llvm-mca` relies on the predicates to be based on `MCSchedPredicate` in order
to resolve the scheduling for variant instructions.  Otherwise, it aborts
the building of the instruction model early.

However, the scheduling model emitter in `TableGen` gives up too soon, unless
all processors use only such predicates.

In order to allow more processors to be used with `llvm-mca`, this patch
emits scheduling transitions if any processor uses these predicates.  The
transition emitted for the processors using legacy predicates is the one
specified with `NoSchedPred`, which is based on `MCSchedPredicate`.

Preferably, `llvm-mca` should instead assume a reasonable default when a
variant transition is not based on `MCSchedPredicate` for a given processor.
This issue should be revisited in the future.

Differential revision: https://reviews.llvm.org/D54648

llvm-svn: 347504
llvm/include/llvm/Target/TargetSchedule.td
llvm/test/tools/llvm-mca/AArch64/CortexA57/shifted-register.s
llvm/test/tools/llvm-mca/AArch64/Cyclone/register-offset.s
llvm/test/tools/llvm-mca/ARM/unsupported-write-variant.s
llvm/utils/TableGen/SubtargetEmitter.cpp