ppc4xx: Optimize PLB4 Arbiter and Memory Queue settings for PPC440SP/SPe,
authorProdyut Hazarika <phazarika@amcc.com>
Wed, 20 Aug 2008 16:38:51 +0000 (09:38 -0700)
committerStefan Roese <sr@denx.de>
Thu, 21 Aug 2008 08:31:16 +0000 (10:31 +0200)
commit079589bcfb24ba11068460276a3cc9549ab5346f
tree85b33c32aaafdedac703834bd763bbf25695f456
parentba37aa03287c5483c61c0a3e320c8888bee0143a
ppc4xx: Optimize PLB4 Arbiter and Memory Queue settings for PPC440SP/SPe,
PPC405EX and PPC460EX/GT/SX

- Read pipeline depth set to 4 for PPC440SP/SPE, PPC405EX, PPC460EX/GT/SX
  processors
- Moved PLB4 Arbiter register definitions to ppc4xx.h since it is shared
  across processors (405 and 440/460)
- Optimize Memory Queue settings for PPC440SP/SPE and PPC460EX/GT/SX
  processors
- Add register bit definitions for Memory Queue Configuration registers

Signed-off-by: Prodyut Hazarika <phazarika@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
cpu/ppc4xx/44x_spd_ddr2.c
cpu/ppc4xx/cpu_init.c
include/asm-ppc/ppc4xx-sdram.h
include/ppc440.h
include/ppc4xx.h