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(parent: 4e718a0) | patch
drm/i915/dp: use 128b/132b TPS2 for UHBR+ link rates
authorJani Nikula <jani.nikula@intel.com>
Thu, 9 Sep 2021 12:51:59 +0000 (15:51 +0300)
committerJani Nikula <jani.nikula@intel.com>
Mon, 20 Sep 2021 15:46:05 +0000 (18:46 +0300)
commit078397bbad2d70cef41771322801b73b39daddb3
treec9257a7a9c249c1f4fec85cf91a15b8685080f83tree | snapshot
parent4e718a0e4053249c0ff5df60f8f3799fce1a1981commit | diff
drm/i915/dp: use 128b/132b TPS2 for UHBR+ link rates

128b/132b channel encoding has separate TPS1 and TPS2, although the DPCD
register values coincide with 8b/10b TPS1 and TPS2 values. Use 128b/132b
TPS2 for channel equalization.

v2: Use intel_dp_is_uhbr

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> # v1
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/723b29223dc570c8b63c3c6fe5fb772d9db06c0d.1631191763.git.jani.nikula@intel.com
drivers/gpu/drm/i915/display/intel_dp_link_training.c diff | blob | history
Domain: System / Kernel;