drm/i915: Do not read non-existent DPLL registers on PCH hardware
authorChris Wilson <chris@chris-wilson.co.uk>
Wed, 2 May 2012 11:07:06 +0000 (12:07 +0100)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 2 May 2012 12:37:51 +0000 (14:37 +0200)
commit074b5e1a99fb5017122591d70098601e0484ca6a
treeca63d7bf7f0700f4a2bffd9da2dbf73977cbcae8
parent69964ea4c7b68c9399f7977aa5b9aa6539a6a98a
drm/i915: Do not read non-existent DPLL registers on PCH hardware

We only execute intel_decrease_pllclock for pre-PCH hardware, typically
gen4 mobiles. However, in the variable declaration we did read from the
non-PCH DPLL register, quite naughty and detected by SandyBridge.

Reported-and-tested-by: Andrey Rahmatullin <wrar@wrar.name>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=49025
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_display.c