drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
authorChaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Mon, 30 Jan 2023 10:08:06 +0000 (15:38 +0530)
committerJani Nikula <jani.nikula@intel.com>
Thu, 16 Feb 2023 10:29:51 +0000 (12:29 +0200)
commit06f1b06dc5b75b1a4071c905231d40cd74587a18
treec452f545264d53654fb94740d89e5e3346f4fe6c
parent61b795a9c35264022cf0bfc49d26e75162a23d5d
drm/i915/display: Add 480 MHz CDCLK steps for RPL-U

A new step of 480MHz has been added on SKUs that have a RPL-U
device id to support 120Hz displays more efficiently. Use a
new quirk to identify the machine for which this change needs
to be applied.

v2: (Matt)
    - Add missing clock steps
    - Correct reference clock typo

v3: - Revert to RPL-U subplatform (Jani)

v4: - Remove Bspec reference from code (Jani)

Bspec: 55409
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230130100806.1373883-3-chaitanya.kumar.borah@intel.com
drivers/gpu/drm/i915/display/intel_cdclk.c