projects / platform / upstream / mesa.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 9fc01f6) | patch
radeonsi: implement two esgs ring nir intrinsic
authorQiang Yu <yuq825@gmail.com>
Mon, 30 May 2022 06:41:08 +0000 (14:41 +0800)
committerQiang Yu <yuq825@gmail.com>
Mon, 27 Jun 2022 03:32:15 +0000 (11:32 +0800)
commit06d493dde22f112754365e35f263cb384ccb7b3b
treece2872012c2e415ef3651f2e936a5374dd0c7a2ctree | snapshot
parent9fc01f6e797161c4385ef60ce57a3c8c5e835742commit | diff
radeonsi: implement two esgs ring nir intrinsic

nir_intrinsic_load_ring_esgs_amd
nir_intrinsic_load_ring_es2gs_offset_amd

Will be used by esgs lowering.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
src/amd/llvm/ac_nir_to_llvm.c diff | blob | history
src/gallium/drivers/radeonsi/si_shader_llvm.c diff | blob | history
Domain: Graphics System / GL;