radeonsi: do Z-only or S-only HTILE clear using a compute shader doing RMW
authorMarek Olšák <marek.olsak@amd.com>
Sun, 21 Mar 2021 20:57:15 +0000 (16:57 -0400)
committerMarge Bot <eric+marge@anholt.net>
Tue, 13 Apr 2021 03:17:42 +0000 (03:17 +0000)
commit06b6af596c2d73410469733d6ef6fe88a3b7248c
tree9f5d57990b4ed05d624c85853c8a4a739ad17fbd
parent84fa21a611b6b80e6effc3aa1df902e49a563500
radeonsi: do Z-only or S-only HTILE clear using a compute shader doing RMW

This adds a clear_buffer compute shader that does read-modify-write to
update a subset of bits in HTILE.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
src/gallium/drivers/radeonsi/si_clear.c
src/gallium/drivers/radeonsi/si_compute_blit.c
src/gallium/drivers/radeonsi/si_pipe.c
src/gallium/drivers/radeonsi/si_pipe.h
src/gallium/drivers/radeonsi/si_shaderlib_tgsi.c