RISC-V: validate riscv,isa at boot, not during ISA string parsing
authorConor Dooley <conor.dooley@microchip.com>
Wed, 7 Jun 2023 20:28:27 +0000 (21:28 +0100)
committerPalmer Dabbelt <palmer@rivosinc.com>
Wed, 21 Jun 2023 14:45:15 +0000 (07:45 -0700)
commit069b0d51707721d5ab2001df866b66b82e4c1c35
tree90a1f48a467c858ce8b0ba66d469efa3c8f5773f
parent2ac874343749b76e069cff5fea09c49e0bd365a0
RISC-V: validate riscv,isa at boot, not during ISA string parsing

Since riscv_fill_hwcap() now only iterates over possible cpus, the
basic validation of whether riscv,isa contains "rv<width>" can be moved
to riscv_early_of_processor_hartid().

Further, "ima" support is required by the kernel, so reject any CPU not
fitting the bill.

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Link: https://lore.kernel.org/r/20230607-guts-blurry-67e711acf328@spud
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
arch/riscv/kernel/cpu.c
arch/riscv/kernel/cpufeature.c