[ARM,MVE] Add the `vshlcq` intrinsics.
authorSimon Tatham <simon.tatham@arm.com>
Tue, 3 Mar 2020 17:37:14 +0000 (17:37 +0000)
committerSimon Tatham <simon.tatham@arm.com>
Wed, 4 Mar 2020 08:49:27 +0000 (08:49 +0000)
commit068b2f313c7d27d9f6445df12d4d45d2d8c00898
treed648735dd74281b6ae0177a8493bbffa4e8c5d59
parent810127f6ab5d5d7e7d6b8c3ae0b96f2027437ca8
[ARM,MVE] Add the `vshlcq` intrinsics.

Summary:
The VSHLC instruction performs a left shift of a whole vector register
by an immediate shift count up to 32, shifting in new bits at the low
end from a GPR and delivering the shifted-out bits from the high end
back into the same GPR.

Since the instruction produces two outputs (the shifted vector
register and the output GPR of shifted-out bits), it has to be
instruction-selected in C++ rather than Tablegen.

Reviewers: MarkMurrayARM, dmgreen, miyuki, ostannard

Reviewed By: miyuki

Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D75445
clang/include/clang/Basic/arm_mve.td
clang/test/CodeGen/arm-mve-intrinsics/vshlc.c [new file with mode: 0644]
llvm/include/llvm/IR/IntrinsicsARM.td
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
llvm/test/CodeGen/Thumb2/mve-intrinsics/vshlc.ll [new file with mode: 0644]