drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend
authorUmesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Tue, 21 Jun 2022 19:21:05 +0000 (12:21 -0700)
committerJohn Harrison <John.C.Harrison@Intel.com>
Mon, 27 Jun 2022 19:21:22 +0000 (12:21 -0700)
commit0667429ce68e0b08f9f1fec8fd0b1f57228f605e
treeccea219b1fdacecc254f358db8bcaaca24322596
parent59bcdb564b3bac3e86cc274e5dec05d4647ce47f
drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend

For execlists backend, current implementation of Wa_22011802037 is to
stop the CS before doing a reset of the engine. This WA was further
extended to wait for any pending MI FORCE WAKEUPs before issuing a
reset. Add the extended steps in the execlist path of reset.

In addition, extend the WA to gen11.

v2: (Tvrtko)
- Clarify comments, commit message, fix typos
- Use IS_GRAPHICS_VER for gen 11/12 checks

v3: (Daneile)
- Drop changes to intel_ring_submission since WA does not apply to it
- Log an error if MSG IDLE is not defined for an engine

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Fixes: f6aa0d713c88 ("drm/i915: Add Wa_22011802037 force cs halt")
Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220621192105.2100585-1-umesh.nerlige.ramappa@intel.com
drivers/gpu/drm/i915/gt/intel_engine.h
drivers/gpu/drm/i915/gt/intel_engine_cs.c
drivers/gpu/drm/i915/gt/intel_execlists_submission.c
drivers/gpu/drm/i915/gt/uc/intel_guc.c
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c