[AArch64] Remove AArch64ISD::NOT, use vnot instead
authorDavid Green <david.green@arm.com>
Wed, 28 Oct 2020 08:15:37 +0000 (08:15 +0000)
committerDavid Green <david.green@arm.com>
Wed, 28 Oct 2020 08:15:37 +0000 (08:15 +0000)
commit066737fdbc8fe22c48649c388ff2421d596ba2a8
tree0a76ddd7fee426ee2507ef72778fa45583764cb0
parentecd4f3fccb04f1968e6ddb0171221a7c28346d4b
[AArch64] Remove AArch64ISD::NOT, use vnot instead

vnot (xor -1) should be equivalent to the AArch64 specific AArch64ISD::NOT
node, but allow more folding thanks to all the target independent
optimizations. Specifically this allows select(icmp ne, x, y) to
become "cmeq; bsl y, x" as opposed to needing to convert the predicate
with "cmeq; mvn; bsl x, y"

Unfortunately there is a regression in a cmtst test, but the code it
selected from was already non-canonical, with instcombine preferring to
use an eq predicate instead. Plus the more common case of icmp ne is
improved.

Differential Revision: https://reviews.llvm.org/D90126
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.h
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/test/Analysis/CostModel/AArch64/vector-select.ll
llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
llvm/test/CodeGen/AArch64/srem-seteq-vec-nonsplat.ll
llvm/test/CodeGen/AArch64/urem-seteq-vec-nonsplat.ll
llvm/test/CodeGen/AArch64/vec_umulo.ll