[Power9] Implement new altivec instructions: permute, count zero, extend sign, negate...
authorChuang-Yu Cheng <cycheng@multicorewareinc.com>
Sat, 26 Mar 2016 05:46:11 +0000 (05:46 +0000)
committerChuang-Yu Cheng <cycheng@multicorewareinc.com>
Sat, 26 Mar 2016 05:46:11 +0000 (05:46 +0000)
commit065969ec8e492eb8f9724492bda55d3ec9b7e68d
tree0865e77923eacbad0f8633a5aaf8bd618ec13f9b
parent01e321306b9f505afa2c15428bfcb2143a70a95f
[Power9] Implement new altivec instructions: permute, count zero, extend sign, negate, parity, shift/rotate, mul10

This change implements the following vector operations:
- vclzlsbb vctzlsbb vctzb vctzd vctzh vctzw
- vextsb2w vextsh2w vextsb2d vextsh2d vextsw2d
- vnegd vnegw
- vprtybd vprtybq vprtybw
- vbpermd vpermr
- vrlwnm vrlwmi vrldnm vrldmi vslv vsrv
- vmul10cuq vmul10uq vmul10ecuq vmul10euq

28 instructions

Thanks Nemanja, Kit for invaluable hints and discussion!
Reviewers: hal, nemanja, kbarton, tjablin, amehsan

Phabricator: http://reviews.llvm.org/D15887
llvm-svn: 264504
llvm/lib/Target/PowerPC/PPCInstrAltivec.td
llvm/lib/Target/PowerPC/PPCInstrFormats.td
llvm/lib/Target/PowerPC/README_P9.txt
llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
llvm/test/MC/PowerPC/ppc64-encoding-vmx.s