[X86] Use MOVQ for i64 atomic_stores when SSE2 is enabled
authorCraig Topper <craig.topper@intel.com>
Sat, 27 Apr 2019 03:38:15 +0000 (03:38 +0000)
committerCraig Topper <craig.topper@intel.com>
Sat, 27 Apr 2019 03:38:15 +0000 (03:38 +0000)
commit063b471ff7fc5b3d7987f2a09279271344f4e6f7
tree4fce604d2f52edc3a188503baf23177be317917b
parent31cfb311c5cbd94963d21a76be8b7c3bec1419cc
[X86] Use MOVQ for i64 atomic_stores when SSE2 is enabled

Summary: If we have SSE2 we can use a MOVQ to store 64-bits and avoid falling back to a cmpxchg8b loop. If its a seq_cst store we need to insert an mfence after the store.

Reviewers: spatel, RKSimon, reames, jfb, efriedma

Reviewed By: RKSimon

Subscribers: hiraditya, dexonsmith, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60546

llvm-svn: 359368
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86ISelLowering.h
llvm/lib/Target/X86/X86InstrAVX512.td
llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
llvm/lib/Target/X86/X86InstrSSE.td
llvm/test/CodeGen/X86/atomic-fp.ll
llvm/test/CodeGen/X86/atomic-load-store-wide.ll
llvm/test/CodeGen/X86/atomic-non-integer.ll
llvm/test/CodeGen/X86/atomic6432.ll