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(parent: b169ef1) | patch
pci: renesas: Fix BAR mapping on Gen3
authorMarek Vasut <marek.vasut+renesas@gmail.com>
Fri, 15 Jan 2021 23:33:17 +0000 (00:33 +0100)
committerMarek Vasut <marek.vasut+renesas@gmail.com>
Sat, 20 Feb 2021 21:38:28 +0000 (22:38 +0100)
commit06183ac5f583d6a6279dd5479cd9b44b7edd9d4c
treecc0d2e5e1414a6237f246ab788c7f1e568b4da64tree | snapshot
parentb169ef17984ff73bee3b4e94844699893971bb8acommit | diff
pci: renesas: Fix BAR mapping on Gen3

Because the first PCIExAR(n) register is configured with the mapping,
It is the second PCIExAR(n) register that must be written with 0, not
the last one. Update the n from 4 to 1 to select the correct register.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
drivers/pci/pci-rcar-gen3.c diff | blob | history
Domain: System / Kernel;