reset: add polarfire soc reset support
authorConor Dooley <conor.dooley@microchip.com>
Fri, 9 Sep 2022 12:31:14 +0000 (13:31 +0100)
committerClaudiu Beznea <claudiu.beznea@microchip.com>
Wed, 14 Sep 2022 07:55:17 +0000 (10:55 +0300)
commit05f9e36370c1517c8e03325f38910fd7ad30b177
tree6c6cd9ece38ac2269ea65b12d851086c569a0fc1
parentb56bae2dd6fda6baf3bb74af3812676eebdd52f2
reset: add polarfire soc reset support

Add support for the resets on Microchip's PolarFire SoC (MPFS).
Reset control is a single register, wedged in between registers for
clock control. To fit with existed DT etc, the reset controller is
created using the aux device framework & set up in the clock driver.

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220909123123.2699583-6-conor.dooley@microchip.com
drivers/reset/Kconfig
drivers/reset/Makefile
drivers/reset/reset-mpfs.c [new file with mode: 0644]