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(parent: 5910955) | patch
x86: quark: Implement PIRQ routing
authorBin Meng <bmeng.cn@gmail.com>
Mon, 25 May 2015 14:35:06 +0000 (22:35 +0800)
committerSimon Glass <sjg@chromium.org>
Thu, 4 Jun 2015 08:39:39 +0000 (02:39 -0600)
commit05b98ec3468547057666dd685b2a1615298c24cc
treef6b4914a6cc6423e573dbf059ce8b8ae057f1659tree | snapshot
parent5910955f3cf685c1ca4e4abd1546fc59da55239acommit | diff
x86: quark: Implement PIRQ routing

Intel Quark SoC has the same interrupt routing mechanism as the
Queensbay platform, only the difference is that PCI devices'
INTA/B/C/D are harcoded and cannot be changed freely.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
arch/x86/cpu/quark/quark.c diff | blob | history
arch/x86/dts/galileo.dts diff | blob | history
arch/x86/include/asm/arch-quark/device.h diff | blob | history
arch/x86/include/asm/arch-quark/quark.h diff | blob | history
configs/galileo_defconfig diff | blob | history
include/configs/galileo.h diff | blob | history
Domain: System / Kernel;